1. Technical Field
The inventive concept relates to semiconductor integrated circuit technology, and more particularly, to a stack memory apparatus.
2. Related Art
With the development of mobile and digital information communication and consumer-electronic industries, conventional devices operating based on control of electron charges in the technical field of mobile and digital information communication may be expected to meet with limits. The development on memory devices with new concept and new functionality other than the devices based on electron charges has been required. In particular, to satisfy the demands on large capacity of the memory device in information handing apparatus, it is necessary to develop next-generation memory devices with large capacity, ultra-high speed, and ultra-low power consumption.
In recent years, as the next-generation memory devices, resistive memory devices using a resistive element as data storage have been suggested. As the next-generation devices, there are typically phase-change random access memory (PCRAM) devices, resistive memory devices, and magnetoresistive memory devices.
The resistive memory device basically includes a switching element and a resistive element. The resistive memory device stores data “1” or “0” according to a resistance stage of the resistive element.
However, the resistive memory device has a critical issue regarding how to improve integration density. There are some concerns about how to integrate memory cells at the maximum in a small area of the resistive memory device.
In the PCRAM device, a diode connected to a word line is used as a switching element. The word line is formed to have a linewidth as narrow as possible to reduce integration density. Accordingly, resistance of the word line is increased. Thus, ‘word line bouncing’ issue may occur to cause an unstable voltage level on the word line.
A structure including memory cells three-dimensionally stacked has been suggested to overcome the word line bouncing. However, because plural memory cells in the stacked memory device are controlled by one bit line or one word line, it may be difficult to separately control cells on each layer.